1. Field of the Invention
The present invention is generally directed to the field of semiconductor processing, and, more particularly, to an improved method for making process films comprised of silicon oxynitride.
2. Description of the Related Art
In the manufacture of semiconductor devices, process films comprised of silicon oxynitride (SiOxNy) are formed at various points during the manufacturing process. By way of example, silicon oxynitride films may be used as an etch stop layer in the formation of conductive interconnections in a semiconductor device. Such layers may also be used to form sidewall spacers adjacent a gate electrode of a semiconductor device and as a metal hard mask layer in ultraviolet photoresist patterning. Such layers are also used for other purposes not enumerated here. One such illustrative situation in which a layer of silicon oxynitride is used as an etch stop layer is depicted in FIGS. 1 and 2 of the attached drawings.
As shown in FIG. 1, a gate stack 12 comprised of a gate conductor 16 and a gate dielectric 14 are formed above a surface 11 of a semiconducting substrate 10. The gate dielectric 14 and the gate conductor 16 are typically made by forming process layers comprised of the appropriate materials above the surface 11 of the substrate 10, and patterning those layers by performing one or more etching processes to define the gate stack 12. Thereafter, the substrate 10 is subjected to a low energy ion implantation process to form lightly doped source/drain extension regions 19 in the substrate 10. Next, a plurality of sidewall spacers 22 are formed adjacent the gate stack 12 by depositing a layer of spacer material and performing one or more anisotropic etching processes to define the sidewall spacers 22. Thereafter, an additional ion implantation process is then performed to complete the formation of the source/drain regions 24 having the familiar lightly doped drain (xe2x80x9cLDDxe2x80x9d) structure.
The fabrication of the transistor is completed by forming appropriate metal contacts through various openings in the layers of dielectric material positioned above the device. In particular, as shown in FIG. 2, a layer of silicon oxynitride 18 may be formed above the structure depicted in FIG. 1, and a dielectric layer 21 may be formed above the layer of silicon oxynitride 18. Thereafter, a plurality of openings 23 are formed in the dielectric layer 21 and the layer of silicon oxynitride 18, and conductive interconnections 25, e.g., conductive plugs, are formed therein.
During this process, the layer of silicon oxynitride 18 serves as an etch stop layer during the formation of the openings 23 in the dielectric layer 21. The material used for the dielectric layer 21 is selectively etchable with respect to the layer of silicon oxynitride 18. Without the use of the silicon oxynitride layer 18 as an etch stop, the underlying source/drain regions 24 may be damaged during the course of forming the openings 23 in the dielectric layer 21. After the openings 23 are formed in the dielectric layer 21, another etching process is performed to remove the layer of silicon oxynitride lying underneath the openings defined in the dielectric layer 21. The etching process used to remove portions of the layer of silicon oxynitride 18 has a high degree of selectivity with respect to the material comprising the dielectric layer 21 and the source/drain regions 24.
Although there are existing techniques for forming the layer of silicon oxynitride 18, the layers resulting from such known techniques or processes exhibit many problems that are detrimental to device performance and integrity. One problem associated with using known techniques for forming silicon oxynitride layers is that such techniques produce unacceptable variations in the thickness of the deposited layer. Such variations in the thickness of the silicon oxynitride layers formed using known techniques and processes may lead to unacceptable results and may create additional problems in subsequent processing operations. For example, localized variations in the thickness of a layer of silicon oxynitride may result in corresponding unevenness in a surface 29 of the dielectric layer 21, although that situation is not depicted in FIG. 2. Such surface non-uniformity may adversely impact the ability to precisely define very small feature sizes in the dielectric layer 21 using photolithographic techniques. Thus, it is very desirable to be able to produce layers of silicon oxynitride with reduced or smaller variations in thickness across the surface of the layer so that these non-uniformities do not propagate to other process layers as they are formed above the layer of silicon oxynitride.
Additionally, in semiconductor processing operations, it is generally desirable to achieve as much throughput as possible to improve yields and reduce costs. This applies equally to the formation of layers of silicon oxynitride. Thus, it is desirable to develop a method of forming layers comprised of silicon oxynitride with an acceptable range of thickness variations while at the same time insuring that deposition rates are as fast as possible to improve production and lower costs.
Another problem associated with the formation of such silicon oxynitride layers is that, in the process of forming such layers, the integrity of the gate dielectric, e.g., gate dielectric 14 in FIG. 1, may be compromised. That is, the breakdown voltage of the gate dielectric, e.g., silicon dioxide, may be reduced below acceptable limits. This in turn may lead to increases in device failure. The damage caused to such gate dielectric may be due, in part, to relatively high power densities used in plasma enhanced chemical vapor deposition processes used to form such layers.
The present invention is directed to solving, or at least reducing, some or all of the aforementioned problems.
The present invention is directed to a method of forming process layers comprised of silicon oxynitride. In one embodiment, the method comprises positioning a wafer in a process chamber, introducing silane and nitrous oxide into the chamber at a flow rate ratio ranging from approximately 2.6-3.8 silane to nitrous oxide, and generating a plasma in the chamber using a high frequency to low frequency power setting ratio ranging from approximately 1.2-1.8.